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A 25 GS/s 6 bit flash interpolating ADC in 90 nm CMOS technology with an analog input bandwidth of 14 GHz is presented. The ADC is realized in a fourfold parallelized structure to increase the sampling rate and to increase the available settling time in the single ADCs. To improve the linearity several calibration methods are implemented in the circuit. The power consumption of the whole ADC is 2.3 W, resulting in a FOM of 1.9 pJ/step. The converter core area is 0.75 mm2.