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Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale as well. We argue that a bottom-up self-assembled fabric will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. In this paper we present a software and hardware framework to measure the performance of a self-configurable computing architecture for unstructured and unknown reconfigurable fabrics composed of simple nodes interconnected by nanowires. The framework allows to create an irregular network of compute nodes where each node can be configured as a simple 1-bit ALU. The compute nodes are organized hierarchically by means of anchor nodes that recruit compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made for 3 different circuits. The hardware overhead of implementing the optimization algorithm is also discussed. The proposed work presents a step toward building a new generation of compute architectures on irregular fabrics.
Date of Conference: 6-9 June 2011