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A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet

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3 Author(s)
Masashi Kono ; Central Res. Lab., Hitachi Ltd., Hitachi, Japan ; Akihiro Kanbe ; Hidehiro Toyoda

A new 400-Gb/s (100-Gb/s×4) physical-layer architecture for the next-generation Ethernet-using 100-Gb/s serial (optical single wavelength) transmission-is proposed. For the next-generation 400-Gb/s Ethernet, there are additional requirements from the market, such as power reduction and further compactization in addition to attaining even higher transmission speed. To meet these requirements, a 100-Gb/s×4 physical-layer architecture is proposed. This architecture uses a 100-Gb/s serial (optical single wavelength) transmission Ethernet and low-power control technologies, which include transmission-capacity-degeneracy control for multi-lane transmission Ethernet. These technologies were implemented on a 100-Gb/s serial (optical single wavelength) transmission Ethernet using a field-programmable gate array (FPGA). Experimental evaluation of this implementation demonstrates the feasibility of low-power and fault-tolerant 400-Gb/s Ethernet.

Published in:

2011 IEEE International Conference on Communications (ICC)

Date of Conference:

5-9 June 2011