By Topic

Short Pulse Generation With On-Chip Pulse-Forming Lines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Yongtao Geng ; Dept. of Electr. & Comput. Eng., Clemson Univ., Clemson, SC, USA ; Huan Zou ; Chaojiang Li ; Jiwei Sun
more authors

We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- μm CMOS process with a 500- μm long PFL, post-layout simulations show that pulses of 10.4-ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4-mm-long PFL is implemented in the commercial 0.13- μm technology. Pulses of ~116-ps duration and 205-300-mV amplitude on a 50-Ω load are obtained when the power supply is tuned from 1.2 to 1.6 V. Measurement connection setup is the main reason for the discrepancies among measurements, modeling, and simulation analyses.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 9 )