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Interconnect Network Analysis of Many-Core Chips

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2 Author(s)
Anant Balakrishnan ; Intel Corporation, Hillsboro, OR, USA ; Azad Naeemi

This paper presents the first intercore interconnect technology optimization and wiring demand calculation for mesh, concentrated mesh, flattened butterfly, and concentrated flattened butterfly network-on-chip topologies. Global wire dimensions are optimized to achieve maximum bandwidth and minimum delay. The core-to-core channel width is then determined by taking into account the available wiring area and area occupied by the router within each core. It is shown that the router area limits the channel width for all topologies. In mesh and concentrated mesh topologies, a smaller channel width results in underutilization of the available wiring area; less than 10% of the area available in two orthogonal wiring levels if the router area is constrained to 20% of the core area. For flattened butterfly and concentrated flattened butterfly topologies, the required wiring areas can be as high as 80% of two orthogonal wiring levels for the same routing area constraint. However, flattened butterfly topology does not scale for a larger number of cores due to the rapid increase in the number of ports and, consequently, router area.

Published in:

IEEE Transactions on Electron Devices  (Volume:58 ,  Issue: 9 )