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A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs

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2 Author(s)
Siozios, K. ; Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece ; Soudris, D.

Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. This letter introduces a TSV-aware partitioning algorithm that enables higher performance for application implementation onto 3-D field-programmable gate arrays (FPGAs). Unlike other algorithms that minimize the number of connections among layers, our solution leads to a more efficient utilization of the available (fabricated) interlayer connectivity. Experimental results show average reductions in delay and power consumption, as compared to similar 3-D computer-aided design (CAD) tools, about 28% and 26%, respectively.

Published in:

Embedded Systems Letters, IEEE  (Volume:3 ,  Issue: 3 )