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Low power digital PLL based TDC using low rate clocks

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8 Author(s)
Park, M.J. ; Dept. of Radio Wave Eng., Hanbat Nat. Univ., Daejeon, South Korea ; Lee, J.Y. ; Boo, H.H. ; Mhin, B.H.
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A time-to-digital converter (TDC) using a low rate clock is presented. A simple TDC, capable of decreasing power consumption and solving the metastability problem by using low-rate clocks to detect the fine fractional time difference between the reference clock and digitally controlled oscillator (DCO) clock, is presented. The proposed TDC also includes a simple DCO clock period (Tv) calculation algorithm. An all-digital phase-locked loop (ADPLL), fabricated in 90 nm CMOS process, dissipates 0.8 mA at 1.2 V, and achieves 6.25 ps period RMS jitter from 2 GHz.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 14 )