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Instruction-level hardware/software partition through DFG exploration

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2 Author(s)
Kang Zhao ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China ; Jinian Bian

To reduce the huge search space when customizing instruction-level accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated instruction-level hardware/software partition method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy. The search space is reduced via considering the performance factors during the identification.

Published in:

Computer Supported Cooperative Work in Design (CSCWD), 2011 15th International Conference on

Date of Conference:

8-10 June 2011