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This brief presents techniques to reduce the blind period of a sampler in high-speed serial link receivers. The impact of the blind period on receiver performance is first investigated. A conventional current-mode logic (CML) master/slave latch-based sampler is reviewed and simulated, followed by the theoretical analysis of the root causes of the sampler blind period. Finally, a proposed sampler is presented with the transistor-level simulation results in a 32-nm silicon-on-insulator process. Operating at 10 Gb/s, the proposed sampler, consuming approximately 25% less current than the conventional CML sampler, exhibits a blind period of approximately 2 ps for the eye height of 40 mV, whereas the conventional CML sampler exhibits a blind period of 33 ps under the same condition.