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New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment

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3 Author(s)
Farid Ghani ; School of Computer and Communication Engineering, University Malaysia Perlis (UniMAP), 02000 Kuala Perlis, Perlis, Malaysia ; Abid Yahya ; Abdul Kader

This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.

Published in:

Computers & Informatics (ISCI), 2011 IEEE Symposium on

Date of Conference:

20-23 March 2011