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Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers

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2 Author(s)
Ching-Hwa Cheng ; Dept. of Electron. Eng., Feng-Chia Univ., Taichung, Taiwan ; Chen-I Chung

There are many test challenges generated from at-speed delay testing requirements. BIST circuit can help to solve traditionally slower ATE tester problems. In this paper, a double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST circuit to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The postlayout simulations that show that the wide-range (26%~76%), fine-scale (16ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning.

Published in:

Dependable Systems and Networks Workshops (DSN-W), 2011 IEEE/IFIP 41st International Conference on

Date of Conference:

27-30 June 2011