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Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames

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2 Author(s)
Basant K. Mohanty ; Dept. of Electronics and Communication Engineering, Jaypee University of Engineering and Technology, Raghogarh, Guna, India ; Pramod K. Meher

In this paper we have presented a memory efficient architecture for 3-D DWT using overlapped grouping of frames. Proposed structure does not involve any line-buffer or frame-buffer for 1-level 3-D DWT. It involves only a frame-buffer of size O(MN) to compute multilevel 3-D DWT, unlike the existing folded structures which involve frame-buffer of size O(MNR) . The saving of line-buffer and frame-buffer by the proposed structure for the implementation of first-level DWT is of substantial advantage, since the frame-size is very often as large as 1920 × 1080 and frame-rate varies from 15 to 60 fps. The proposed structure has a small cycle period, and offers small output latency compared to the existing structures. Compared to the best of the available designs, the proposed design involves significantly less memory words. For frame-size 17 × 144 and frame-rate 60 fps, the proposed structure involves 7.96 times less memory words and involves 12.3% less average computation time (ACT) than the best of the existing folded designs. It involves 4.28 times less memory words than the recently proposed parallel design. The synthesis result for frame-size 176 × 144 and frame-rate 60 fps for the FPGA device 6VLX760FF1760-2 shows that the proposed structure involves 9.6 times less BRAMs and offers 2 times higher throughput than the folded design. It involves 1.9 times less BRAMs than the parallel design and offers nearly same throughput rate. The proposed structure has significantly less slice-delay-product (SDP) and dissipates significantly less dynamic power than the existing structures.

Published in:

IEEE Transactions on Signal Processing  (Volume:59 ,  Issue: 11 )