Referenced Items are not available for this document.
We propose a new test generation method for F-scan delay fault testing that uses standard full scan delay fault automatic test pattern generation (ATPG). This method shows that it is possible to generate test patterns fast for F-scannable register-transfer level (RTL) circuits by using currently well-developed and high-performance commercial ATPG tools for gate-level scan circuits.
Published in:
European Test Symposium (ETS), 2011 16th IEEE
Date of Conference: 23-27 May 2011
- Page(s):
- 203
- ISSN :
- 1530-1877
- E-ISBN :
- 978-0-7695-4433-5
- Print ISBN:
- 978-1-4577-0483-3
- INSPEC Accession Number:
- 12135900
- Conference Location :
- Trondheim
- Digital Object Identifier :
- 10.1109/ETS.2011.61
- Product Type:
- Conference Publications
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