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F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG

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3 Author(s)
Marie Engelene J. Obien ; Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan ; Satoshi Ohtake ; Hideo Fujiwara

We propose a new test generation method for F-scan delay fault testing that uses standard full scan delay fault automatic test pattern generation (ATPG). This method shows that it is possible to generate test patterns fast for F-scannable register-transfer level (RTL) circuits by using currently well-developed and high-performance commercial ATPG tools for gate-level scan circuits.

Published in:

2011 Sixteenth IEEE European Test Symposium

Date of Conference:

23-27 May 2011