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The paper proposes a new hierarchical untestable stuck-at fault identification method for non-scan sequential circuits containing feedback loops. The method is based on deriving, minimizing and solving test path activation constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path activation constraints for a module under test. Then, the constraints are minimized and a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the tool is capable of quickly proving a large number of untestable faults obtaining high fault efficiency. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.
European Test Symposium (ETS), 2011 16th IEEE
Date of Conference: 23-27 May 2011