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Active Clamping Circuit to Suppress Switching Stress on a MOS-Gate-Structure-Based Power Semiconductor for Pulsed-Power Applications

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4 Author(s)
Bongseong Kim ; Dept. of Electr. Eng., Hanyang Univ., Seoul, South Korea ; Heung-Jin Ju ; Kwang-Cheol Ko ; Hotta, E.

Metal-oxide-silicon (MOS)-gate-structure-based power semiconductors, such as MOS field-effect transistors, insulated-gate bipolar transistors, and MOS controlled thyristors, are widely used as high-voltage switch and power modulator components in pulsed-power applications. The power semiconductors are generally connected in series and in parallel in order to increase their maximum switching voltage and current, respectively. It is important to suppress overvoltage or switching stress on power semiconductors connected in series and parallel during an extremely short switching time and at fast operating frequency. Generally, gate drive control techniques and methods for the suppression of high voltage are required. To suppress overvoltage and switching stress, this paper proposes a simple and effective active clamping method rather than the use of a snubber circuit with free switching condition modulation. Based on comparative switching experiments, the active clamping method is expected to suppress switching stress and overvoltage while load and switching conditions are changed without modification of the high-side auxiliary circuit for pulsed-power applications.

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Plasma Science, IEEE Transactions on  (Volume:39 ,  Issue: 8 )