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Study on High Throughput Turbo Decoder

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2 Author(s)
Jaesung Choi ; Sch. of Electr. & Electron. Eng., Chung-Ang Univ., Seoul, South Korea ; Jeong Woo Lee

Turbo codes have outstanding error correction performance. However, the implementations of the iterative turbo decoder require substantial memory and incur a long latency which cannot be tolerated in some applications. In this paper, various kinds of high throughput turbo decoding schemes are introduced, and we propose a new turbo decoding scheme that using the advantages of each scheme. The proposed scheme is basically based on the sliding window, double flow and shuffled turbo decoding scheme. Simulation results show that the proposed scheme offers good BER performance with less clock cycles per iteration than existing turbo decoding schemes. We also show that the required memories can be reduced by adjusting the size of window properly.

Published in:

Vehicular Technology Conference (VTC Spring), 2011 IEEE 73rd

Date of Conference:

15-18 May 2011

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