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In this paper, a new low-power profile for mixed-signal design of SARADC is presented. In this profile, frequency dependency of the design power rather than the conventional supply voltage is emphasized. According to this frequency dependency, a new method for low power design in the mixed-signal domain is presented. In this method whole system is divided into clocked parts and non clocked parts subsystem. Accordingly, a new formula for power consuming in the mixed signal domain is offered. Evaluation results show that when the frequency of a mixed signal system drops down, the ratio of power consumption in analog and digital units have different patterns. In this respect, for our target study of SARADC the power share in analog is about constant while the share of digital sections is rapidly reduced. This means that to reduce the total power, the analog section must be redesigned. The SARADC has a major analog unit as a comparator. In this paper, a new comparator is developed that reduced the analog part share from 89% at 100 KHz to 72% at 100 KHz. The frequency of the target design is selected in range 50 KHz–200 KHz, which is the conventional range of operations for ADC in Wireless Sensor Network (WSN) nodes. Therefore, proposed new SARADC design is fully suitable for WSN node applications. The proposed SARADC is designed and simulated in 90nm CMOS with the total average power of 4.96μW at 100 KHz.