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A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.
Circuits and Systems Workshop (DCAS), 2010 IEEE Dallas
Date of Conference: 17-18 Oct. 2010