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In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.
Date of Conference: 23-25 May 2011