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In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.
Published in:
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Date of Conference: 23-25 May 2011
- Page(s):
- 259 - 262
- ISSN :
- 0195-623X
- E-ISBN :
- 978-0-7695-4405-2
- Print ISBN:
- 978-1-4577-0112-2
- INSPEC Accession Number:
- 12120610
- Conference Location :
- Tuusula
- Digital Object Identifier :
- 10.1109/ISMVL.2011.11
- Product Type:
- Conference Publications
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