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This paper presents a graph-based approach to designing multiple-valued arithmetic circuits. Our method describes arithmetic circuits in a hierarchical manner with high-level multiple-valued graphs, which are determined by specific algebra and arithmetic formulae. The proposed circuit description can be effectively verified by symbolic computations such as polynomial reduction using Groebner Bases. In this paper, we describe the proposed graph representation and show an example of its description and verification. The advantageous effects of the proposed approach are demonstrated through experimental designs of parallel multipliers over Galois field GF(2m) for different word-lengths and irreducible polynomials. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits where the conventional simulation techniques failed.
Date of Conference: 23-25 May 2011