Referenced Items are not available for this document.
In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology.
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:59
,
Issue:
1
)
Date of Publication: Jan. 2012
- Page(s):
- 159 - 169
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 12444113
- Digital Object Identifier :
- 10.1109/TCSI.2011.2158704
- Product Type:
- Journals & Magazines
- Date of Publication :
- 14 July 2011
- Date of Current Version :
- 09 January 2012
- Issue Date :
- Jan. 2012
- Sponsored by :
- IEEE Circuits and Systems Society
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