By Topic

Minimizing the search space for computing exact worst-case delays of AFDX periodic flows

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Muhammad Adnan ; Université de Toulouse/IRIT/ENSEEIHT/INPT 2, rue Camichel, 31000 Toulouse, France ; Jean-Luc Scharbarg ; Christian Fraboul

AFDX (Avionics Full Duplex Switched Ethernet) standardized as ARINC 664 is a major upgrade for avionics systems. Guarantees on worst case end-to-end communication delays are required for certification purposes. These guarantees are obtained thanks to safe upper bounds computed by Network Calculus and Trajectory Approaches. Indeed, up to now, the computation of an exact worst case delay is intractable, except for very small configurations (less than 10 virtual links (VLs)). This paper proposes an algorithm which significantly increases the size of the configuration for which an exact worst case delay can be obtained (up to 50 VLs). This is achieved, thanks to a drastic reduction of the search space. For larger configurations (up to 100 VLs) the algorithm can be adapted to obtain reachable values for the end-to-end delay which are close to the exact worst case. Generalization to industrial configurations (more than 1000 flows) is under way.

Published in:

2011 6th IEEE International Symposium on Industrial and Embedded Systems

Date of Conference:

15-17 June 2011