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This paper presents an alternative technique for the adaptive control of power electronic converter circuits. Specific attention is given to the adaptive control of a dc-dc converter. The proposed technique is based on a simple adaptive filter method and uses a one-tap finite impulse response (FIR) prediction error filter (PEF). The method is computationally efficient and based around a dichotomous coordinate descent (DCD) algorithm. The DCD-recursive least squares (RLS) algorithm has been employed as the adaptive PEF to reduce the computational complexity of existing RLS algorithms for efficient hardware implementation. Results show that the DCD-RLS is able to improve the dynamic performance and convergence rate of the adaptive gains (filter taps) within the controller. In turn, this yields a significant improvement in the overall dynamic performance of the closed-loop control system, particularly in the event of abrupt parameter changes. The proposed controller uses an adaptive proportional-derivative+integral (PD +I) structure which, alongside the DCD algorithm, offers an effective substitute to a conventional proportional-integral-derivative (PID) controller. The nonadaptive integral controller (+I), introduced in the feedback loop, increases the excitation of the filter tap weight and ensures good regulation. The approach results in a fast adaptive controller with self-loop compensation. This is required to minimize the prediction error signal and, in turn, minimize the voltage error signal in the loop by automatically calculating the optimal pole locations. The prediction error signal is further minimized through a second-stage FIR filter (adaptation gain stage). This ensures that the adaptive gains converge to their optimal value. This paper presents detailed simulation analysis and experimental validation on a prototype synchronous dc-dc buck converter. The experimental results clearly demonstrate the superior dynamic performance and voltage regulation compa- - red to conventional PID and adaptive LMS control schemes, with only a modest increase in the computational burden to the microprocessor.