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A low latency high throughput router for On-Chip interconnect networks

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2 Author(s)
Jinwen Li ; Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China ; Shubo Qi

A low latency high throughput Dynamic Virtual Output Queues Router for On-Chip interconnect networks is proposed in this paper, which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output queues scheme. Compared to wormhole router and virtual channel router, Simulation results show that network throughput on a 4×4 mesh increases by up to 46.□2 and 81.62 respectively, and outperforms doubled buffer virtual channel by N□2 under same input speedup, z etwork 5ero-load-latency also decreases by 8T.62 and 4N2 respectively under random traffic. Synthesis results in MS0 C 6Tnm technology indicate the frequency of router with G4G4mm8 area can reach 8.THF 5.

Published in:

Computer Science and Automation Engineering (CSAE), 2011 IEEE International Conference on  (Volume:1 )

Date of Conference:

10-12 June 2011