Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays

Field-Programmable Gate Arrays (FPGAs) are considered as the assertive digital implementation medium as measured by design starts. The ability for designers to avoid the pitfalls of Nanoelectronic design and changing the design until last minute made FPGAs more demanding in recent years. But consumption of much area and power has been contemplated as the major drawback for FPGAs over Application Specific ICs (ASIC). In this paper, we have designed the logic block of a Plessey FPGA in reversible manner with reduced number of reversible gates, garbage outputs and quantum cost. As reversible computing reduces the power consumption of any system, this design approach will definitely resolve the power problem for FPGAs. Our proposed design uses the most cost effective reversible circuits including proposed 3*3 MG (MUX Gate) in comparison with the existing ones in literatures.