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Static analysis of run-time inter-thread interferences in shared cache multi-core architectures based on instruction fetching timing

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3 Author(s)
Fangyuan Chen ; Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China ; Dongsong Zhang ; Zhiying Wang

For real-time systems, in order to provide the basis for schedulability analysis, it is crucial to obtain Worst-Case Execution Time (WCET) of applications, which is very challenging due to the possible runtime inter-thread interferences caused by shared resources in multi-core processors. For multi-core platforms with shared cache, instructions of a thread may be evicted by another co-running thread, which results in the interferences in shared cache. Designers need to consider the interferences while analyzing WCET of threads on multi-core platforms. This paper proposes a novel approach to analyzing the worst-case cache interferences based on instruction fetching timing, while judging the interferences status through instruction fetching timing relations. The paper presents an algorithm for instruction fetching timing based on Depth-First-Search in control flow graph. Our approach can reasonably estimate runtime inter-thread interferences in shared cache by introducing timing relations analysis into address mapping method. Experiments show that our proposed approach improves the tightness of WCET estimation by 19.244% on average.

Published in:

Computer Science and Automation Engineering (CSAE), 2011 IEEE International Conference on  (Volume:2 )

Date of Conference:

10-12 June 2011