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Concurrent Error Detection Adder Based on Two Paths Output Computation

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4 Author(s)
Khedhiri, C. ; Electron. & Microelectron.''Lab., Monastir, Tunisia ; Karmani, M. ; Hamdi, B. ; Ka Lok Man

This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to avoid the problem of extra time we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. The proposed design involves 12.12% saving in transistor count compared to DMR (Dual Modular Redundancy) style design.

Published in:

Parallel and Distributed Processing with Applications Workshops (ISPAW), 2011 Ninth IEEE International Symposium on

Date of Conference:

26-28 May 2011