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Prevention flow-control for low latency torus networks-on-chip

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2 Author(s)
Joshi, A. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Madras, Chennai, India ; Mutyam, M.

The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. We describe a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure freedom from deadlock. Flow-control is achieved using a prevention mechanism which uses virtual cut-through switching, and deadlock freedom is achieved by considering only a single packet buffer per input port. We can simplify the router design by having a simple switch allocator, which prioritizes insight packets, and a single packet buffer per input port, which eliminates the need for virtual channels. Experimental validation reveals that our design achieves significant improvement in throughput, as compared to the traditional design, using significantly fewer buffers.

Published in:

Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on

Date of Conference:

1-4 May 2011

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