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Competitive density, performance, and functional objectives of the SRAM bit cell require design rules which are much more aggressive than those used in base logic designs. Because soft fail yield in SRAM is dependent on the device threshold and threshold mismatch in the bit cell, much research has been directed toward addressing the random contributors to within-cell device threshold variation. We examine four sources of potential nonrandom threshold mismatch that can arise from the use of aggressive design rules in the bit cell: 1) implanted ion straggle in SiO2; 2) polysilicon inter-diffusion driven counter-doping; 3) lateral ion straggle from the photoresist; and 4) photoresist implant shadowing. Using simulation and hardware measurements, we quantify the device parametric impacts and provide a statistical treatment forming the basis for quantification of the functional margin impacts on the bit cell. We examine two lithography-compliant bit-cell layout topologies and quantify the impact of systematic mismatch on the margin limited yield.