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On optimal board-level routing for FPGA-based logic emulation

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2 Author(s)
Wai-Kei Mak ; Dept. of Comput. Sci., Texas Univ., Austin, TX, USA ; Wong, D.F.

In this paper, we consider a board-level routing problem which is applicable to field-programmable gate arrays (FPGA)-based logic emulation systems such as the Realizer System and the Enterprise Emulation System manufactured by Quickturn Design Systems. For the case where all nets are two-terminal nets, we present an O(n2)-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of interchip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iterative computation of Euler circuits in graphs. We also prove that the routing problem with multiterminal nets is NP-complete. Also we suggest one way to handle multiterminal nets using some additional resources

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:16 ,  Issue: 3 )