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Stress Effects on Self-Aligned Silicon Nanowire Junctionless Field-Effect Transistors

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6 Author(s)
C. J. Huang ; Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan ; C. H. Yang ; C. Y. Hsueh ; J. H. Lee
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The heavily doped n-type silicon nanowire (SiNW) junctionless field-effect transistors (JLFETs) are fabricated using the self-aligned process to control the position and direction of SiNWs. Aligned SiNWs are grown across the prepatterned source and drain under the assistance of the externally applied electric field, which facilitates the subsequent device fabrication. The JLFET exhibits an electron mobility of ~90 cm2/V·s, an on/off ratio of ~107, and a subthreshold slope of ~100 mV/dec. Furthermore, the current variation under stress is investigated. It is shown that stress-induced current change reaches maximum when the JLFET is operated in pinchoff condition. Finally, improvement of off current by 98% and subthreshold swing by 15% using compressive stress of 100 MPa in the n-type JLFET is achieved.

Published in:

IEEE Electron Device Letters  (Volume:32 ,  Issue: 9 )