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KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer

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3 Author(s)
S. Chattopadhyay ; Dept. of Comput. Sci. & Technol., Deemed Univ., Agra, India ; S. Roy ; P. P. Chaudhuri

In the domain of combinational logic synthesis, logic minimization plays a vital role in determining the area and performance of the synthesized circuit. Logic minimization based on AND-OR decomposition of functions is a well studied area. However, minimization based on AND-XOR decomposition has received relatively lesser attention. Since many real-life combinational functions are XOR dominated, a logic minimizer producing efficient AND-XOR decomposition can lead to more efficient realization of such circuits. The computer-aided design tool KGPXORMIN presented in this paper is a multilevel AND-XOR minimizer which outperforms the scheme reported by Saul (1991) by 45.77% in the literal count metric. In general, most of the real-life and benchmark circuits are a combination of OR and XOR logic. In order to have area efficient realization, we need to have an efficient minimizer capable of judicious use of OR and XOR gates. An integrated tool KGPMIN has been developed which combines the AND-XOR minimizer KGPXORMIN and well-known AND-OR minimizer MISII. Depending on the measure of dominance of OR and XOR logic, it switches from one minimizer to the other during the decomposition phase. By judicious switching from one minimizer to the other, on the average, KGPMIN outperforms MISII by 64.08% in literal count and 45.16% in absolute gate area for the MCNC combinational logic benchmarks. It also outperforms KGPXORMIN by 17.46% in literal count and 34.32% in gate area. The number of levels of the circuits synthesized with KGPMIN can be found to be comparable with the figures arrived at from the application of MISII

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:16 ,  Issue: 3 )