A methodology based on Transportation problem modeling for designing parallel interleaver architectures

For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each memory bank has to be performed without any conflict. The consideration applies to the two main classes of turbo-like codes: Low Density Parity Check (LDPC) and Turbo-Codes. In this paper, we present an original approach based on Transportation problem modeling which finds conflict free memory mapping for every type of turbo codes and which optimizes the resulting interleaving architecture.