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Fourier domain decoding algorithm of non-binary LDPC codes for parallel implementation

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2 Author(s)
Kasai, K. ; Tokyo Inst. of Technol., Tokyo, Japan ; Sakaniwa, K.

For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worse, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

Published in:

Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on

Date of Conference:

22-27 May 2011