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Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations

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6 Author(s)
Joonho Kong ; Div. of Comput. & Commun. Eng., Korea Univ., Seoul, South Korea ; Yan Pan ; Ozdemir, S. ; Mohan, A.
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Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 8 )

Date of Publication:

Aug. 2012

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