Skip to Main Content
In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.