By Topic

Optimized embedding of an incomplete binary tree in a two-dimensional array of programmable logic blocks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chrzanowska-Jeske, M. ; Dept. of Electr. Eng., Portland State Univ., OR, USA ; Yang Xu

This paper describes an efficient scheme for embedding an incomplete binary tree, representing a combinational circuit, in a two-dimensional array of programmable logic blocks. This problem appears in layout-driven logic synthesis for combinational circuits which are implemented with fine-grain locally connected Field Programmable Gate Arrays (FPGAs). We use an efficient data structure and node sorting algorithm to restructure the binary tree such that the mapping process is simplified. The mapping of the restructured tree is performed such that no routing blocks are inserted into the longest paths, and the area occupied by the mapped tree is minimized. A comparison between previous methods and ours is shown using the ATMEL 6000 FPGA series as a target architectures

Published in:

Circuits and Systems, 1996., IEEE 39th Midwest symposium on  (Volume:1 )

Date of Conference:

18-21 Aug 1996