Optimized embedding of an incomplete binary tree in a two-dimensional array of programmable logic blocks

This paper describes an efficient scheme for embedding an incomplete binary tree, representing a combinational circuit, in a two-dimensional array of programmable logic blocks. This problem appears in layout-driven logic synthesis for combinational circuits which are implemented with fine-grain locally connected Field Programmable Gate Arrays (FPGAs). We use an efficient data structure and node sorting algorithm to restructure the binary tree such that the mapping process is simplified. The mapping of the restructured tree is performed such that no routing blocks are inserted into the longest paths, and the area occupied by the mapped tree is minimized. A comparison between previous methods and ours is shown using the ATMEL 6000 FPGA series as a target architectures.