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In this paper, we describe an efficient Xilinx Spartan3A DSP implementation of 2D DWT (Discrete Wavelet Transforms) using polyphase filterbank architecture with Distributed Arithmetic (DA) to speedup wavelet computation. Results show that the distributed arithmetic formulation results in a considerable performance gain while reducing the consumption of logic resources significantly. This architecture supports any size of Image and any level of decomposition. With minor changes this core can be implemented on any FPGA device. This irreversible Discrete Wavelet Transform uses 9/7 Daubechies coefficients which are used for lossy compression in the JPEG2000 standard. We can plug this core directly in any JPEG ENCODER / TV display controller for any crontel device (BT656 standard, interface of CH7009).
Electronics Computer Technology (ICECT), 2011 3rd International Conference on (Volume:1 )
Date of Conference: 8-10 April 2011