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Multi-objective optimization of power, area and delay during high-level synthesis of DFG's — A genetic algorithm approach

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3 Author(s)
Logesh, S.M. ; Dept. of Electron. & Commun. Eng., Amrita Vishwa Vidyapeetham Univ., Coimbatore, India ; Ram, D.S.H. ; Bhuvaneswari, M.C.

High-level synthesis (HLS) involves the translation of behavioural algorithmic descriptions into an RTL implementation. The parameters to be optimized in high-level synthesis such as power, area and delay are mutually conflicting necessitating trade-offs during the implementation. For complex designs, the design space to be explored is vast. This paper proposes a weighted sum genetic algorithm for optimization of datapaths during high-level synthesis using graded penalty cost function to perform simultaneous scheduling and allocation. GAs being population based, are ideal for searching the large solution space involved. The proposed technique has been evaluated on HLS DSP benchmark circuits like IIR filter and DCT filter and has been found to yield better power aware solutions than a single objective GA, simultaneously optimizing area and delay. The framework provides a large number of alternative datapath designs, all of which meet user design specifications but differ in module, register and interconnect configurations. An average of about 15.7% power reduction on DCT filter and 13% power reduction on IIR filter were obtained.

Published in:

Electronics Computer Technology (ICECT), 2011 3rd International Conference on  (Volume:1 )

Date of Conference:

8-10 April 2011