By Topic

A dynamic timing delay for accurate gate-level circuit simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tang, T. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore ; Zhou, X.

A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models

Published in:

Circuits and Systems, 1996., IEEE 39th Midwest symposium on  (Volume:1 )

Date of Conference:

18-21 Aug 1996