By Topic

Towards “zero-energy” using NEMFET-based power management for 3D hybrid stacked ICs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Voicu, G.R. ; Fac. of EE, Math. & CS, Delft Univ. of Technol., Delft, Netherlands ; Enachescu, M. ; Cotofana, S.D.

In this paper we describe and evaluate a 3D hybrid power management architecture which makes use of Nano-Electro-Mechanical Field Effect Transistors (NEMFET) as power switches that cut-off the power supply of inactive blocks. 3D stacking combines the appealing extremely low leakage currents of the NanoFETs with the versatility of CMOS technology by allowing for the power switches to be fabricated on a separate die. This simplifies the power planning in general, allows for always-on blocks to also be implemented with NEMFETs, and can increase the computation platform performance because of extra area cleared by the switches. Moreover it leverages the integration of other NEMS/MEMS devices, e.g., energy harvesters, sensors, on the same layer with the power switches. To validate this proposal and evaluate its performance in a real-life scenario we perform a careful assessment of the implications of this hybrid power management architecture on the rest of the system. To this end we consider the 3D embodiment of an embedded openMSP430 processor based SoC platform running a bio-medical sensing application for heart rate detection and measure the effects of the 3D hybrid architecture on sensitive metrics used in power gating designs, e.g., delay degradation, power-up and power-down behavior, and overall energy consumption. Our experiments indicate that, due to the extreme low leakage current of the NEMFETs, the system idle energy is decreased by 2.74x at the expense of a 4x area overhead on the NEMS tier. Moreover, due to the 3D hybrid approach the energy-delay product of the embedded SoC platform is reduced by 9%, with a potential improvement of up to 60% for applications with lower activity, e.g., wireless sensor networks. Last but not least the 3D stacked architecture prevents clock period degradation issues, since the IR Drop is reduced with a factor of 4x. Based on our experiment we believe that such 3D hybrid NEMS/CMOS approach creates the premises for the substantia- - l reduction of an increasingly important component of the total energy consumption, the leakage power while idle, thus it makes nanosystems meet the limited energy budget of local energy harvesters, and become potentially autonomous “zero-energy” devices.

Published in:

Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on

Date of Conference:

8-9 June 2011