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A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits

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3 Author(s)
Yao Wang ; Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands ; Cotofana, S. ; Liang Fang

As planar MOSFETs is approaching its physical scaling limitation, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a unified reliability model of Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) for double-gate and triple-gate FinFETs, towards a practical reliability assessment method for future FinFETs based circuits. The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures. Apart of introducing the reliability model we also investigate the circuit performance degradation due to NBTI and HCI in order to create the premises for its utilization for assessing and monitoring the Integrated Circuits (ICs) aging process. To validate our model we simulated NBTI and HCI degradation and compared the obtained Vth shift prediction with the one evaluated based on experimental data. The simulations suggest that our model characterize the NBTI and HCI process with accuracy and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.

Published in:

Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on

Date of Conference:

8-9 June 2011