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Low-power functionality enhanced computation architecture using spin-based devices

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6 Author(s)
Augustine, C. ; Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Panagopoulos, G. ; Behin-Aein, Behtash ; Srinivasan, Srikant
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Power consumption in CMOS integrated circuits increases every technology generation due to increased subthreshold and gate leakage currents. To cope with such a problem, researchers have started looking at the possibility of logic devices based on electron spin, as an alternative to charge based CMOS, for realizing low-power integrated circuits with low active power dissipation and zero standby leakage. In this paper, we investigate spin-based logic devices that employ low-power spin-torque switching mechanism for circuit operation. We have developed a Functionality Enhanced All Spin Logic (FEASL) architecture and a synthesis framework using Logically Passively Self Dual (LPSD) formulation. This methodology enables the design of large functional logic blocks, especially low-power adders and multipliers, which constitute the building blocks of all arithmetic logic units (ALU). In addition, we have investigated three different variants of ASL, which are low-power, medium-power-medium performance and high performance and we analyze their merits and drawbacks at circuit/architecture level. We synthesized Discrete Cosine Transform (DCT) algorithm using adders and multipliers to show the efficacy of the proposed FEASL approach in designing digital signal processing (DSP) systems. Compared to 15nm CMOS implementation, the FEASL based DCT shows 88% improvement in power and 83% in PDP with 43% degradation in performance.

Published in:

Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on

Date of Conference:

8-9 June 2011

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