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Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures

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2 Author(s)
Koohi, S. ; Comput. Eng. Dept., Sharif Univ. of Technol., Tehran, Iran ; Hessabi, S.

This paper proposes new architectures for data and control planes in a nanophotonic networks-on-chip (NoC) with the key advantages of scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the data network which leads to small and simple photonic switches. Built upon the proposed novel topology, we present a scalable all-optical NoC, referred to as 2D-HERT, which offers passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method, Wavelength Division Multiplexing (WDM) technique, and a new all-optical control architecture, our proposed optical NoC eliminates the need for optical resource reservation at the intermediate nodes and the corresponding latency and area overheads. We compare performance of the proposed architecture against electrical NoCs and alternative all-optical architectures under various synthetic traffic patterns. Averaging through different traffic patterns, 2D-HERT architecture reduces data transmission delay by 18%, 4%, and 70% and achieves average per-packet power reduction of 53%, 45%, and 95% over optical crossbar, λ-router, and electrical Torus, respectively.

Published in:

Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on

Date of Conference:

8-9 June 2011

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