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Nanofabric power analysis: Biosequence alignment case study

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4 Author(s)
Frache, S. ; Electron. Dept., Politec. di Torino, Torino, Italy ; Amaru, L.G. ; Graziano, M. ; Zamboni, M.

The promising features of Nanoscale array structures pave the way for interesting applications like biosequence alignment, that currently can be addressed only at the price of a huge overhead in terms of area and power dissipation. Nanofabrics, once technology will be mature enough, are expected to enormously overcome these limits, and assure an evident advantage in terms of processing capabilities.Therefore biosequence alignment is our case study in this work and we use the NanoASIC (NASIC) as target platform. We developed an event based simulator which works at nano-wire FET (nwFET) level to evaluate logic behavior. Here it evolved so that a detailed switching activity of simple library gates could be found in order to evaluate their power dissipation. This is devised using accurate ballistic nwFET models to fully characterize nwFET on and off characteristics and gate capacitance. From our results it is evident an underestimation of these values if quantum effects are not taken into account. We then proposed an architectural solution to a biosequence alignment problem, based on the concurrent execution of identical processing elements (PE) instanced in an arbitrary number. Performance in terms of power, area, timing and processing capabilities were found for a single processing element as a function of several design and technological parameters. The design solution space was then explored considering an increasing number of parallel PE. The expected improvements in terms of power, area and timing with respect to solutions proposed using currently available technology have been underlined. From one to three orders of magnitude is the expected improvement in terms of processing capability (depending on the possible technological scenarios), with a power dissipation reduction from 3 to 12 times, respectively.

Published in:

Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on

Date of Conference:

8-9 June 2011

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