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Regular 2D NASIC-based architecture and design space exploration

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4 Author(s)
Ciprian Teodorov ; Lab-STICC CNRS UMR 3192, Université de Bretagne Occidentale, Brest, France ; Pritish Narayanan ; Loic Lagadec ; Catherine Dezan

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

Published in:

2011 IEEE/ACM International Symposium on Nanoscale Architectures

Date of Conference:

8-9 June 2011