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A 3D Network-on-Chip for stacked-die transactional chip multiprocessors using Through Silicon Vias

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2 Author(s)
Kumar, S.S. ; Circuits & Syst. Group, Delft Univ. of Technol., Delft, Netherlands ; van Leuken, R.

Effective utilization of computing power offered by modern chip multiprocessors (CMP) depends on the design and performance of the interconnect that connects them. We present a three-dimensional Network-on-Chip (NoC) based on the R3 router architecture for transactional CMPs utilizing advanced Through Silicon Vias (TSV) in a stacked-die architecture, facilitating low latency and high throughput communication between CMP nodes. We report the performance of an R3 based three-dimensional mesh in a stacked-die transactional CMP highlighting the limitations of performance scale-up with stacking. Furthermore, we present data on area penalty associated with the use of TSVs in different configurations in 90nm UMC technology.

Published in:

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on

Date of Conference:

6-8 April 2011