By Topic

A new method for noise analysis in nano-scale VLSI circuits using wavelet

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Haghayegh, A. ; Assoc. of Electr. & Electron. Eng., Islamic Azad Univ., Tehran, Iran ; Forouzandeh, B. ; Fathi, D. ; Kangarloo, K.

This paper analyzes signals in nanometer VLSI circuits using wavelet techniques; afterwards, noise source (aggressor line) and interconnect effects are studied. As becoming integrated circuits denser, using nanometer scale technologies, shrinking dimensions of interconnects, the role of interconnect parasitic effects in the signal integrity at high speeds, become increasingly significant which may result in the aggravation of crosstalk noise amplitude and duration, and the circuit faults. Using wavelet transform techniques in signal analysis and several simulations of the interconnect output signals, the proposed wavelet-based approach precisely and also clearly defines which interconnects are considered as the victim lines and which ones as the aggressor lines, and each interconnect can also be numbered. The effect of both the series resistance and the output parasitic capacitance of the driver has been taken into account for an accurate modeling of the VLSI interconnect line.

Published in:

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on

Date of Conference:

6-8 April 2011