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The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. Examples of 3D-SICs include 3D CMOS sensors, 3D FPGAs, 3D processors, 3D cache and memory, and combined stacks of memories and processors. 3D-SICs can be manufactured using three different stacking approaches: Wafer-to-Wafer (W2W), Die-to-Wafer (D2W) or Die-to-Die (D2D) stacking. Each stacking approach has its benefits and drawbacks. The major benefit of W2W is the high manufacturing throughput and the ability to handle small dies. However, it suffers from low compound yield. In D2D a high yield can be obtained due to Known Good Die (KGD) stacking, but the throughput is expected to be low. The manufacturing throughput in D2W settles between D2D and W2W, and results in similar yields as in D2D due to the same ability of KGD stacking. This talk will address two major challenges in 3D-SIC manufacturing: yield improvement and test cost reduction. First, it will investigate wafer matching as a mean to improve the overall compound yield for W2W stacking. In wafer matching, wafers with the same or similar faulty die distribution are stacked in order to minimize the number of faulty stacks. A framework covering different matching processes and wafer matching criteria for both replenished and non-replenished wafer repositories will be presented. From this framework, different scenarios are analyzed. The simulation results show that the compound yield not only depends on the number of stacked dies, die yield, and repository size, but it also strongly depends on the used matching process and the wafer matching criteria. Moreover, by choosing the appropriate wafer matching scenario the compound yield can be significantly improved relative to random W2W stacking. Second, the impact of the- - different test flows on the overall 3D D2W staked IC will be investigated and analyzed. D2W stacking has the advantage of KGD stacking, but opens new avenues for testing. Every manufactured chip has to be tested, and any tiny test saving per 3D-SIC impacts the overall cost, especially in high-volume production. It is self-evident that many possible intermediate tests (e.g. interconnect test, die test) are possible when stacking 3D-SICs. A framework covering different test flows for D2W stacking will be presented. In addition, a cost model will discussed and used to investigate the impact of the test cost for different test flows. The simulation results show that (a) test flows with pre-bond testing significantly reduce the overall cost, (b) a cheaper test flow does not necessary result in lower overall cost, (c) test flows with intermediate tests (performed during the stacking process) pay off, (d) the most cost-effective test flow consists of pre-bond tests and strongly depends on the stack yield; hence, adapting the test according the stack yield is the best approach to use.