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Hardware/software co-designed accelerator for vector graphics applications

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6 Author(s)
Shuo-Hung Chen ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Hsiao-Mei Lin ; Hsin-Wen Wei ; Yi-Cheng Chen
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This paper proposes a new hardware accelerator to speed up the performance of vector graphics applications on complex embedded systems. The resulting hardware accelerator is synthesized on a field-programmable gate array (FPGA) and integrated with software components. The paper also introduces a hardware/software co-verification environment which provides in-system at-speed functional verification and performance evaluation to verify the hardware/software integrated architecture. The experimental results demonstrate that the integrated hardware accelerator is fifty times faster than a compiler-optimized software component and it enables vector graphics applications to run nearly two times faster.

Published in:

Application Specific Processors (SASP), 2011 IEEE 9th Symposium on

Date of Conference:

5-6 June 2011